1. Field
An aspect of the embodiments discussed herein is directed to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits formed on semiconductor substrates have a device isolation structure called shallow trench isolation (STI), as well as smaller transistors and finer wiring, to increase the packing density.
For example, Japanese Laid-open Patent Publication No. 2007-109966 and No. 2005-243928 discuss semiconductor devices having an STI transistor.
In an STI structure, an insulating layer is embedded in a semiconductor substrate by the following process.
As illustrated in FIG. 30A, a first silicon oxide layer 102 and a silicon nitride layer 103 are sequentially formed on a silicon substrate 101. A resist pattern 104 covering an active region is then formed on the silicon nitride layer 103.
The silicon nitride layer 103, the first silicon oxide layer 102, and the silicon substrate 101 are etched using the resist pattern 104 as a mask. As illustrated in FIG. 30B, after a device isolation trench 105 is formed around the active region of the silicon substrate 101, the resist pattern 104 is removed. A second silicon oxide layer (not illustrated) is then formed on the surface of the device isolation trench 105.
The device isolation trench 105 is entirely filled with a third silicon oxide layer formed by chemical vapor deposition (CVD). As illustrated in FIG. 30C, the third silicon oxide layer on the silicon substrate 101 is removed by chemical mechanical polishing (CMP) using the silicon nitride layer 103 as a polish stop layer. The third silicon oxide layer remaining in the device isolation trench 105 constitutes an STI structure 106. The silicon nitride layer 103 is then selectively removed by wet etching.
As illustrated in FIG. 30D, an N-type MOSFET 111 is formed on the active region of the silicon substrate 101 surrounded by the STI structure 106.
A process for forming the N-type MOSFET 111 includes the operations of forming a P-well 108 in the active region of the silicon substrate 101, forming a gate oxide 109 and a gate electrode 111g on the silicon substrate 101, forming sidewalls 110 on the gate electrode 111g, and forming a source region 111s and a drain region 111d in the silicon substrate 101 by n-type impurity ion implantation before and after the formation of the sidewalls 110.
Although not illustrated in the drawings, another active region is doped with an n-type impurity to form an N-well. A P-type MOSFET is formed in this active region.
In the processes for forming a P-well and an N-well, the application of a resist, impurity ion implantation, and removal of the resist are sequentially performed to define an impurity ion implanted region. A solution to remove the resist also removes part of the STI structure 106. Furthermore, when a sacrificial oxide layer (not illustrated) on the silicon substrate 101 is removed with hydrogen fluoride after the P-well and the N-well are formed, the STI structure 106 is partly removed.
Japanese Laid-open Patent Publication No. 2007-109966 discusses that, when an oxide layer on a silicon substrate is etched with hydrogen fluoride, edges of an active region of the silicon substrate be not exposed, that is, an STI structure be higher than the surface of the silicon substrate.
Since an STI structure is formed of silicon oxide, a difference in thermal expansion coefficient between silicon oxide and a silicon substrate may cause a stress between a device isolation trench and an active region.
This stress affects a channel-forming region under a gate electrode. As illustrated in FIG. 30D, a variation in the distance X between the gate electrode 111g and the STI structure 106, that is, the widths of the source region 111s and the drain region 111d, may result in a variation in a source-drain current running under the gate electrode 111g. 
FIG. 2 in Japanese Laid-open Patent Publication No. 2005-243928 discusses that, relative to the on-state current of a MOSFET having a sufficiently long source-drain distance X, the on-state current of a P-type MOSFET gradually increases as the distance X becomes smaller than a predetermined value, and the on-state current of an N-type MOSFET gradually decreases as the distance X becomes smaller than a predetermined value.
An increase in on-state current may result in a decrease in threshold voltage and, in an actual semiconductor circuit, an increase in standby leakage current larger than expected. On the other hand, a decrease in on-state current may result in an increase in threshold voltage and, in an actual semiconductor circuit, an increase in operation delay time larger than expected. In addition, the characteristics of an N-type or P-type MOSFET vary significantly with the source or drain width. This imposes a further restriction in design.
In Japanese Laid-open Patent Publication No. 2005-243928, it is discussed that, in a circuit including a first and second transistors, a distance X between a gate electrode and one end of each of active regions in which the first and second transistors are disposed be constant to prevent variations in on-state current due to variations in distance X. However, in a high-density semiconductor circuit design, it is sometimes desirable to make the distance between a gate electrode and an adjacent device isolation trench constant to equalize the on-state current in all of the MOSFETs constituting a semiconductor integrated circuit. FIG. 18 in Japanese Laid-open Patent Publication No. 5-129533 discusses that the threshold voltage of a P-type MOSFET increases as the distance X becomes larger than a predetermined value.